The $135M Bet That AI’s Real Bottleneck Is Memory, Not Processing Power

Cyprus Business Group · Technology & Investment Desk

A chip startup founded by former Samsung and SK Hynix engineers has closed a major funding round on the premise that the AI industry has been solving the wrong problem all along.

A structural flaw in the way AI thinks

Every interaction with a large language model sets off a hidden relay race inside server infrastructure. A user’s query leaves memory, passes through a central processing unit for preparation, travels to a graphics processing unit for intensive computation, and then returns — and this entire sequence repeats for every word the model produces in response.

This is not an engineering quirk that can be patched. It is a structural inefficiency baked into the design of modern AI hardware — one that routes every operation through some of the most power-hungry and expensive components in the industry. For hyperscalers running billions of queries each day, the cumulative cost is enormous.

XCENA’s answer: bring compute to the data

Korean-American startup XCENA has spent four years engineering a different approach. Rather than sending data back and forth between memory and processors, the company has developed a chip that positions computational capability directly alongside DRAM — the high-speed, short-term memory modules that store information a processor is actively working with. Routine data operations are handled within the memory module itself, dramatically reducing costly round-trip journeys across the system.

The company’s flagship product, the MX1, connects to a central processor via CXL (Compute Express Link) — a dedicated high-speed lane between processor and memory — intercepting and processing data before it ever needs to leave the memory module.

“CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that.” — Jin Kim, CEO

The implications, if proven at scale, are striking. XCENA claims that workloads previously requiring ten servers could potentially be handled by a single unit.

The memory architecture shift investors are funding

XCENA has closed a $135 million Series B at a valuation of $570 million, bringing its total capital raised to $185 million. The round was co-led by Seoul-based VC firms Atinum and IMM Investment, alongside Corstone Asia and existing backers SBI Investment and Mirae Asset Capital. The company is also in discussions with international investors regarding further funding.

The timing aligns with a notable shift in global memory markets. This month, Samsung, SK Hynix, and Micron — the three companies that collectively dominate worldwide memory chip supply — each crossed a trillion-dollar valuation for the first time, reflecting surging demand for memory solutions since the second half of last year.

“The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures.” — Jin Kim, CEO

What the chip actually does differently

While GPUs remain the dominant tool for matrix multiplication — the heavy mathematical workload at the core of AI model training — much of the surrounding infrastructure work still runs on CPUs. This includes preprocessing, KV cache management (the system that stores prior conversation context so a model does not have to repeatedly reprocess it), and data caching.

“Our chip handles those tasks directly within the memory module itself.” — Jin Kim, CEO

XCENA’s architecture is built on RISC-V, an open-source chip design framework, and features thousands of small, highly efficient processing cores optimised for data throughput. The company also designs its own internal memory hierarchy, interconnect bus, and DRAM controller — a degree of vertical integration that most chip companies, including larger rivals, typically outsource to third parties.

Market position and the road to production

XCENA is targeting the memory-intensive layer that underpins all AI inference workloads — a segment distinct from the NPU and GPU competition centred on training. Its closest publicly listed competitors include Astera Labs and Marvell, both working on next-generation memory connectivity.

Kim acknowledges Marvell as a well-established player in the space, but argues the differentiator is intellectual property depth. Where Marvell’s approach relies on a small number of general-purpose cores, XCENA has engineered thousands of purpose-built cores for this specific task.

The MX1 remains a prototype. Mass production chips are scheduled to come off Samsung’s foundry lines by the end of 2026, with revenue generation targeted from 2027. The company’s ideal customer base is the global tier of hyperscalers investing tens of billions annually in AI infrastructure — organisations where even marginal gains in memory efficiency can translate to hundreds of millions in savings.

The company, which employs over 90 staff across offices in Pangyo — a technology hub outside Seoul — and Sunnyvale, California, is also in early-stage conversations with several global memory vendors, though Kim declined to name them.

“Inference isn’t just a compute problem; it’s increasingly a memory scaling problem.” — Jin Kim, CEO